There exists a continuing need to improve semiconductor device performance and further scale semiconductor devices. A characteristic that limits scalability and device performance is electron and hole mobility, also referred to as channel mobility, throughout the channel region of transistors. As devices continue to shrink in size, the channel region for transistors continues to also shrink in size, which can limit channel mobility.
One technique that may improve scaling limits and device performance is to introduce strain into the channel region, which can improve electron and hole mobility. Different types of strain, including expansive strain, uniaxial tensile strain, and compressive strain, have been introduced into channel regions of various types of transistors in order to determine their affect on electron and/or hole mobility. For some devices, certain types of strain improve mobility whereas other types degrade mobility.
Turning briefly to FIG. 1 illustrated is a cross-sectional view of a semiconductor device 100 at a stage of fabrication wherein a tensile stress is introduced by a conventional cap-annealing process. The semiconductor device 100, which happens to be an n-channel metal oxide semiconductor (NMOS) device, includes a substrate 110 having a well region 120 located therein. The semiconductor device 100 of FIG. 1 further includes a gate structure 130 located over the substrate 110. The gate structure 130, as appreciated, includes both a gate dielectric layer 133 and a gate electrode layer 138.
Positioned on both sides of the gate structure 130 are source/drain sidewall spacers 140. The source/drain sidewall spacers 140 illustrated in FIG. 1 each include only a single sidewall spacer. Positioned in the substrate 110 proximate the gate structure 130 are source/drain regions 150. The source/drain regions 150 therefore define a channel region 160 in the substrate 110.
After the source/drain regions 150 have been formed by implanting a suitable dopant, such as arsenic in the instant case, a stress-inducing layer 170 is deposited over the substrate 110 and gate structure 130. Among other processes, a chemical vapor deposition (CVD) process could be used to form the stress-inducing layer 170. Generally, the temperature of the deposition should be lower than the phase transition temperature of amorphous silicon. Then, a rapid thermal anneal is performed at a relatively high temperature, introducing and locking stress 180a, 180b into the channel region 160. The stress-inducing layer 170 is then removed and silicide regions (not shown) are typically formed on the source/drain regions 150 and gate electrode layer 138. A suitable silicide process is a conventional cobalt, nickel or other similar metal salicide process.
Compressive stress from the gate electrode layer 138 is enhanced by the annealing process described above, which introduces tensile stress 180a, 180b across the channel region 160. This tensile stress 180a, 180b can improve the performance of the semiconductor device 100 by improving hole and electron mobility in the channel region 160. The cap-annealing process described supra can show improvement for, among others, NMOS devices.
Unfortunately, it has been observed that the aforementioned process is unable to easily and accurately tune the stresses 180a, 180b, within the channel region 160. Moreover, it has been observed that the stresses 180a, 180b are generally detrimental to the channel mobility of p-channel metal oxide semiconductor (PMOS) devices. Furthermore, because of the manufacturing processes used to form the stress-inducing layer 170, it is difficult to form such a layer only over the NMOS devices. The aforementioned process also introduces more process steps which increase the cost of manufacturing.
Accordingly, what is needed in the art is an improved method for manufacturing a semiconductor device, and a device manufactured using that method, that does not experience the aforementioned problems.